Digital Audio Broadcasting (DAB) is the third generation of broadcasting after amplitude modulation (AM) and frequency modulation (FM) broadcasting. Compared with current broadcasting, DAB has the advantages of good sound quality (CD quality), multimedia and high-speed mobile reception, encryption, low transmission power, large coverage area, high spectrum utilization, and strong anti-interference ability. The services transmitted by DAB can be diverse. In addition to regular audio programs, it can also transmit any form of other data, such as text, still images, or live audio and video. Therefore, DAB is also known as Digital Multimedia Broadcasting (DMB). This article mainly
This article introduces the software and hardware design of the DAB transmission system encoder based on PC and Cyclone II EP2C20F484C7 FPAG, which fully considers the requirements of circuit scale and resource utilization. This design is intended for testing DAB/DMB receivers.
Design of Encoder for DAB Transmission System
The transmission system of DAB mainly includes a source encoder located at the program provider position, a multiplexer located at the broadcasting station position, and a COFDM (Coding Orthogonal Frequency Division Multiplexing) encoder modulator located at the transmission position, where COFDM can be further divided into channel coding and OFDM modulation. The encoder at the DAB transmitter mainly includes a frame decoding module for ETI (Service Group Transmission Interface), a channel encoding module, a DQPSK modulation module, an OFDM modulation module, an up conversion module, a digital filtering module, a USB interface module, etc. The channel coding module includes energy diffusion, removable convolutional coding, time interleaving, frequency interleaving, etc. The input of the entire encoder is ETI frames from the multiplexer, and the output is an analog intermediate frequency signal.
The entire design mainly consists of software coding on the PC side, IFFT module design on the FPGA side, and PCB design for USB and DAC modules. The PC end mainly implements the demultiplexing of ETI frames, channel coding, and DQPSK modulation. The modulated data is transmitted to the FPGA end through the USB interface, and the FPGA end receives the data and hands it over to the IFFT module for IFFT transformation. This is the main method for implementing OFDM (Orthogonal Frequency Division Multiplexing). The data output by IFFT is converted from baseband signal to intermediate frequency by IF up converter, and then sent to DAC module after digital filtering. Afterwards, the DAC module converts the digital signal into an analog signal and sends it to the transmitter for transmission. The frequency can be selected from BANDIII (165-240Mhz) to L-band (1452-1492Mhz).
PC software design
The PC software mainly implements the demultiplexing of ETI frames, channel coding (including energy diffusion, convolutional coding, time interleaving, frequency interleaving), and DQPSK modulation. At the same time, USB data transfer and USB module control are achieved through the driver program provided by the manufacturer, and a PC human-machine interface is provided. Users can select the ETI program to be transmitted and set its transmission mode.
Encoder PC interface
Encoder PC interface
(1) Explanation of ETI frame: An ETI frame mainly includes frame header information (related information of the frame and each sub channel within the frame) and main service flow data MST (including audio data stream and fast data channel FIC). Firstly, we need to extract the synchronization information and frame length information of the incoming ETI frame in order to locate the frame header. Based on the ETI frame format, extract FIC information and main business data flow information.
(2) Channel coding: The FIC data and main service flow data extracted from ETI frames are energy diffused, and then based on the extracted protection level information of each sub channel, each service component is subjected to removable convolutional coding according to the protection level. Then, the main service data is time interleaved, and the interleaved main service data is combined into the CIF frame of the main service channel (MSC). The FIC information is not time interleaved and is combined with the CIF frame to form the DAB transmission frame. Meanwhile, frequency interleaving of DAB transmission frames has also been implemented on the PC end.
(3) DQPSK modulation: After frequency interleaving of data information, DQPSK modulation is performed based on the initial phase of each carrier to obtain the modulation phase information of each carrier.
(4) USB transmission control: The DQPSK modulated DAB frames are transmitted to the IFFT hardware module on the FPGA through the USB interface. Write the corresponding USB data transfer program based on the USB driver provided by the manufacturer.
Design of FPGA end
The FPGA mainly implements IFFT (inverse Fourier transform) operation, IF up converter, and digital filter. Perform IFFT operation on the phase information of DAB frames transmitted from the PC to complete OFDM modulation, and then convert the modulated baseband signal into an intermediate frequency signal through a frequency converter, filter it, and send it to the DAC module. Due to the need to receive data from the USB module, an additional USB interface module is required on the FPGA. At the same time, an internal RAM is required as a buffer between the USB interface module and the IFFT module. After the IFFT operation, the data is stored in a 2048 * 24 bit dual port RAM space, and after frequency conversion and filtering, it is output to the DAC module through the DAC interface module. The IFFT operation module, USB interface module, up conversion module, and DAC interface module are controlled by the NIOSII soft core processor embedded in ALTERA, and a SOPC (SystemOn Programmable Chip) system is built on FPGA.
FPGA design framework
Considering the resources occupied by this design, including logical units and embedded memory, in order to achieve full utilization of resources, ALTERA's Cyclone II series FPGA EP2C20 development board was selected. This board has 512KByte of off chip RAM space, which can be used as NIOS program memory and USB interface data buffer to ensure real-time data transmission. After the comprehensive design of each module in FPGA, it occupies more than 15000 logic units (including NIOSII module) and 82% (52 M4K) of memory bits. The entire system uses a clock of 65.536MHz, effectively utilizing the resources of the development board and achieving good results.
PCB design
The design of PCB includes two parts: USB module and DAC module.
(1) The USB module is mainly used to achieve high-speed communication between PC and FPGA. Considering that the transmission speed needs to reach 300KB/s to achieve real-time data transmission, FT245BL is selected as the USB interface chip
(2) The DAC module is designed to convert the digital signal output by the digital filter into an analog signal. The encoder outputs a digital intermediate frequency signal with a sampling frequency of 16.384MHz and a bandwidth of 1.536MHz. After being converted into an analog signal through DAC, it needs to be amplified, filtered, and output as a DAB analog intermediate frequency signal with a peak to peak value of 1V.
Summary of this article
This article introduces the design of a DAB transmission system encoder based on PC and FPGA. The channel coding of the DAB transmission system before OFDM modulation is implemented through software. Through experimental testing, it can perform real-time channel coding on a 2.048Mb/s ETI data stream. At the same time, the data rate transmitted to the OFDM module on the FPGA through the USB interface can reach 320KB/s, meeting the real-time requirements. Afterwards, the analog signal output by the DAC module is sent to the DAB transmitter through the SMA connector. Figure 4 shows the physical encoder of the DAB transmission system. It has been proven that placing the channel coding part on the PC side is a simple and effective implementation method, and using FPGA to implement the channel coding part will be the next step.
